Morgan Stanley's latest research report indicates that Google's self-developed Frozen v2 chip may not use TSMC's CoWoS advanced packaging technology, and plans to directly integrate SRAM into the chip's silicon. In terms of packaging technology, the industry currently believes that TSMC's CoWoS package is more suitable for high-performance AI chips, while Intel's EMIB-T is generally regarded as more suitable for high-end AI chips, but the latest research reports suggest that Google may abandon packaging and directly integrate SRAM into chip silicon. The advantage of this solution is that it has extremely high bandwidth and ultra-low latency, but it also faces huge challenges of increasing die area, power consumption, and heat dissipation.

Morgan Stanley's latest research report indicates that Google's self-developed Frozen v2 chip may not use TSMC's CoWoS advanced packaging technology, and plans to directly integrate SRAM into the chip's silicon. In terms of packaging technology, the industry currently believes that TSMC's CoWoS package is more suitable for high-performance AI chips, while Intel's EMIB-T is generally regarded as more suitable for high-end AI chips, but the latest research reports suggest that Google may abandon packaging and directly integrate SRAM into chip silicon. The advantage of this solution is that it has extremely high bandwidth and ultra-low latency, but it also faces huge challenges of increasing die area, power consumption, and heat dissipation.