On August 4, local time, at the 2026 Future Storage and Memory Conference held in Santa Clara, USA, Samsung Electronics announced the next-generation storage technology route for AI infrastructure, first showcased ZHBM and Znand-O concept products, and launched 400-layer V10 BV-NAND using wafer bonding technology. Samsung said that ZhBM aims to shorten the data transmission distance between the processor and memory by stacking the HBM vertically on top of the AI accelerator to improve AI training and inference performance. ZhBM equipped with a next-generation interface system is expected to achieve about 8 times the performance of HBM5. At the same time, using new wafer bonding technology, it can achieve memory density 10 times higher than HBM5 and improve energy efficiency performance. In the NAND field, Samsung released the V10 BV-NAND architecture for the first time. The storage units are stacked using wafer bonding technology. The number of layers exceeds 400 layers, increasing the memory density by about 58% compared to the previous generation of V9 products, while improving read/write and input/output performance.

On August 4, local time, at the 2026 Future Storage and Memory Conference held in Santa Clara, USA, Samsung Electronics announced the next-generation storage technology route for AI infrastructure, first showcased ZHBM and Znand-O concept products, and launched 400-layer V10 BV-NAND using wafer bonding technology. Samsung said that ZhBM aims to shorten the data transmission distance between the processor and memory by stacking the HBM vertically on top of the AI accelerator to improve AI training and inference performance. ZhBM equipped with a next-generation interface system is expected to achieve about 8 times the performance of HBM5. At the same time, using new wafer bonding technology, it can achieve memory density 10 times higher than HBM5 and improve energy efficiency performance. In the NAND field, Samsung released the V10 BV-NAND architecture for the first time. The storage units are stacked using wafer bonding technology. The number of layers exceeds 400 layers, increasing the memory density by about 58% compared to the previous generation of V9 products, while improving read/write and input/output performance.