On August 12, Synopsys announced the verification of the world's first HBM4 IP test chip. Eye diagram results obtained from the test chip showed that the system achieved stable and reliable operation at a rate of 9.2 Gbps. In addition, the HBM4 IP test chip has completed interconnection verification with the HBM memory chip. The scope of verification covers not only PHY itself, but also interface architecture design, signal transmission scheme, and compatibility with real HBM DRAM. Currently, many customers have begun to use Synopsys HBM4 IP solutions.

On August 12, Synopsys announced the verification of the world's first HBM4 IP test chip. Eye diagram results obtained from the test chip showed that the system achieved stable and reliable operation at a rate of 9.2 Gbps. In addition, the HBM4 IP test chip has completed interconnection verification with the HBM memory chip. The scope of verification covers not only PHY itself, but also interface architecture design, signal transmission scheme, and compatibility with real HBM DRAM. Currently, many customers have begun to use Synopsys HBM4 IP solutions.