As AI agents and trillion-parameter workloads become increasingly mainstream, the performance of AI infrastructure depends not only on computing power, but also on how computing, memory, storage, networks, and software are collaboratively designed as a unified system. To help hyperscale enterprises and AI innovators build next-generation semi-customized AI infrastructures, NVIDIA introduced NVIDIA NVHBM technology, further expanding the NVIDIA NVLink Fusion technology solution. NVHBM is a new generation of high-bandwidth memory technology that provides XPU with higher memory performance and efficiency. The technology will be validated and delivered by leading memory partners to benefit NVLink Fusion customers with this advanced memory capability. By integrating the memory controller into the 3D HBM stack rather than the XPU, the NVHBM can achieve up to 30% increase in memory bandwidth compared to the standard HBM4E, reduce HBM power consumption by 15%, and free up as much as 25% of the area for the XPU calculation die.

As AI agents and trillion-parameter workloads become increasingly mainstream, the performance of AI infrastructure depends not only on computing power, but also on how computing, memory, storage, networks, and software are collaboratively designed as a unified system. To help hyperscale enterprises and AI innovators build next-generation semi-customized AI infrastructures, NVIDIA introduced NVIDIA NVHBM technology, further expanding the NVIDIA NVLink Fusion technology solution. NVHBM is a new generation of high-bandwidth memory technology that provides XPU with higher memory performance and efficiency. The technology will be validated and delivered by leading memory partners to benefit NVLink Fusion customers with this advanced memory capability. By integrating the memory controller into the 3D HBM stack rather than the XPU, the NVHBM can achieve up to 30% increase in memory bandwidth compared to the standard HBM4E, reduce HBM power consumption by 15%, and free up as much as 25% of the area for the XPU calculation die.