On October 14, Interface News learned that Mingxin Qirui recently announced the completion of the “Taishan 1” streaming film for the first high-density, high-capacity RRAM chip based on the 1tnR technology route, and is currently advancing chip verification. The chip uses a 28nm CMOS process platform and 1T4R storage structure. The single chip has a capacity of 1Gb, a storage density of 30MB/mm², an access delay of less than 20ns, and an integrated on-chip hardware error correction circuit. It is reported that the 1T4R structure connects four resistance storage units through a selective transistor to increase storage density.

On October 14, Interface News learned that Mingxin Qirui recently announced the completion of the “Taishan 1” streaming film for the first high-density, high-capacity RRAM chip based on the 1tnR technology route, and is currently advancing chip verification. The chip uses a 28nm CMOS process platform and 1T4R storage structure. The single chip has a capacity of 1Gb, a storage density of 30MB/mm², an access delay of less than 20ns, and an integrated on-chip hardware error correction circuit. It is reported that the 1T4R structure connects four resistance storage units through a selective transistor to increase storage density.