Japan's Ministry of Economy, Trade and Industry approved the TSMC Kumamoto Plant 2 production plan change plan submitted by TSMC and its Japanese subsidiary JASM. According to the preliminary plan approved in February 2024, the plant's main products are logic semiconductors using 6nm and 12nm processes, and it is planned to support 40nm process production according to the needs of the Japanese domestic market. The entire plant has a monthly production capacity of 63,000 wafers. The revised plan will use 3nm process logic semiconductors as the main product, with a monthly production capacity of 6,000 wafers. The first batch of products is expected to be shipped in the fourth quarter of 2028, and production is planned to continue for more than 10 years. The products will mainly be delivered to Japanese customers. On the same day, changes to the production plan for the Kumamoto Plant 1 were also approved. The original plan was to use logic semiconductors using 22/28nm and 12/16nm processes as the main product, but the revised plan removed the 12/16nm process and used the 22/28nm process as the main product.

Japan's Ministry of Economy, Trade and Industry approved the TSMC Kumamoto Plant 2 production plan change plan submitted by TSMC and its Japanese subsidiary JASM. According to the preliminary plan approved in February 2024, the plant's main products are logic semiconductors using 6nm and 12nm processes, and it is planned to support 40nm process production according to the needs of the Japanese domestic market. The entire plant has a monthly production capacity of 63,000 wafers. The revised plan will use 3nm process logic semiconductors as the main product, with a monthly production capacity of 6,000 wafers. The first batch of products is expected to be shipped in the fourth quarter of 2028, and production is planned to continue for more than 10 years. The products will mainly be delivered to Japanese customers. On the same day, changes to the production plan for the Kumamoto Plant 1 were also approved. The original plan was to use logic semiconductors using 22/28nm and 12/16nm processes as the main product, but the revised plan removed the 12/16nm process and used the 22/28nm process as the main product.