According to a report by South Korea's ZDNet on November 10, Samsung Electronics plans to complete the development of the next-generation advanced packaging technology 3D Cube-H in early 2027, launch the first design toolkit, and then launch a potential customer evaluation. The technology uses hybrid bonding to achieve vertical chip stacking through direct connection between copper and copper. The interconnection spacing target is about 6 microns, which is significantly smaller than the minimum spacing of 25 microns in Samsung's existing hot pressing contract. Compared with traditional technology, hybrid bonding can increase chip connection density, improve heat dissipation, and reduce data transmission energy consumption. It is suitable for high-performance AI chips, GPU stacking, and integration of logic chips with HBM. Samsung hopes to use this to enhance the competitiveness of advanced packaging and create conditions to obtain AI chip OEM orders from large technology companies.

According to a report by South Korea's ZDNet on November 10, Samsung Electronics plans to complete the development of the next-generation advanced packaging technology 3D Cube-H in early 2027, launch the first design toolkit, and then launch a potential customer evaluation. The technology uses hybrid bonding to achieve vertical chip stacking through direct connection between copper and copper. The interconnection spacing target is about 6 microns, which is significantly smaller than the minimum spacing of 25 microns in Samsung's existing hot pressing contract. Compared with traditional technology, hybrid bonding can increase chip connection density, improve heat dissipation, and reduce data transmission energy consumption. It is suitable for high-performance AI chips, GPU stacking, and integration of logic chips with HBM. Samsung hopes to use this to enhance the competitiveness of advanced packaging and create conditions to obtain AI chip OEM orders from large technology companies.